An optimized test ports selecting method under power constraint in NoC
功耗限制下的NoC测试端口的优化选择方法

An optimized test ports selecting method was proposed, in which the number and location of input/output pairs under power constraint could be determined. To make the length of all the core test paths shortest, the optimized location of the Network on Chip (NoC) test ports were selected. With the constraint of the max permitted power in the test, the number of the test ports pairs was chosen as large as possible. Thus the test of the cores could be accomplished with high performance, and the apparatus damage in the test could be avoided effectively. Experimental results show that the efficiency of the test is improved and the overall cost in the NoC test is decreased.