%0 Journal Article
%T An optimized test ports selecting method under power constraint in NoC<br>功耗限制下的NoC测试端口的优化选择方法
%A OUYANG Yi-ming
%A FENG Wei
%A LIANG Hua-guo
%A <br>欧阳一鸣
%A 冯伟
%A 梁华国
%J 计算机应用
%D 2008
%I 
%X An optimized test ports selecting method was proposed, in which the number and location of input/output pairs under power constraint could be determined. To make the length of all the core test paths shortest, the optimized location of the Network on Chip (NoC) test ports were selected. With the constraint of the max permitted power in the test, the number of the test ports pairs was chosen as large as possible. Thus the test of the cores could be accomplished with high performance, and the apparatus damage in the test could be avoided effectively. Experimental results show that the efficiency of the test is improved and the overall cost in the NoC test is decreased.
%K System on Chip (Soc)
%K Network on Chip (NoC)
%K Test Access Mechanism (TAM)<br>片上系统
%K 片上网络
%K 测试访问机制
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=8240383F08CE46C8B05036380D75B607&jid=831E194C147C78FAAFCC50BC7ADD1732&aid=65D26A5700C9B6CC9B150F9043A9B7BC&yid=67289AFF6305E306&vid=D3E34374A0D77D7F&iid=E158A972A605785F&sid=8E4B4A74C5BF6530&eid=5CC11A326E54A79A&journal_id=1001-9081&journal_name=计算机应用&referenced_num=0&reference_num=10