Loop based trace way prediction for instruction cache
基于循环的指令高速缓存访问预测方法

This paper proposed a new scheme of way prediction, named loop based trace way prediction, for instruction cache, to decrease the access power. The scheme made loop the premise of starting way prediction. By recording the trace of cache access when it encountered a loop, it could predict the way when getting in the same loop. Also made a research on multiple-trace way prediction scheme to get a better hit rate. Experiment results from Powerstone show this scheme can get a hit rate of 99%. On average it can decrease 65% power dissipation compared to conventional set-associative cache, and increase only 0. 2% the time to access cache.