A Extension Bit Method for Parallel Frame Synchronous Scrambler
并行帧同步扰码器的扩充比特设计法

Based on parallel recursive synchronous scramble method, an novel extension bit method for parallel frame synchronous scrambler is proposed. Using periodicity of the scramble sequence, it is theoretic proved the complexity of this method is not depended on the expression of generation polynome. This method does not need to calculate recursive formula of the parallel scrambler. It makes the design of scrambler and descrambler simple. The memory depth of scramler is only relative to the rank of the generation polynome. The arbitrary word-wide scrambler can be constitute with the memory a few read/write logic.It is high efficence and low logical complexity proved by FPGA designing, and this mothed has been applied in the front terminal of high-speed optical transport system.