VLSI Design of the Low-Power Rake Receiver for Wireless Sensor Networks
无线传感网低功耗Rake接收机VLSI设计与实现

A low-power VLSI Rake receiver is proposed and realized on FPGA for wireless sensor networks used in complicated wireless environments. Low-power design strategies including reducing clock frequency, sharing of models and dynamic sleeping control are used to reduce the power consumption in order to fit the energy limitations in wireless sensor networks. Simulations and applications show that the receiver can specially reduce VLSI resource and power consumption compared to ordinary Rake receiver.