A Power-Conversion Rate Merit Model for High-Speed High-Resolution ADC
适于高速高精度多级ADC的功耗-速率优值模型

Based on multi-stage comparison, a new theory incorporating Minimum Comparator Number Algorithm (MCNA) and Power-Conversion Rate Merit Model (PCRMM) is proposed, which releases the power dissipation from limitation of comparators, sub-DACs and residual amplifiers in high-speed high-resolution ADCs. Under 10-bit ADC resolution specific, theoretical analysis shows that this theory reduces the power dissipation of Flash ADC to minimum by applying 3-stage Pipelined ADC, while keeping ADC high-speed, and it also proves that two-step ADC is better than other type of multi-step ADC. This new theory can be used in designing and developing high-speed low-power ADCs.