%0 Journal Article
%T A Power-Conversion Rate Merit Model for High-Speed High-Resolution ADC<br>适于高速高精度多级ADC的功耗-速率优值模型
%A Wu Shuang-yi
%A Yu Qi
%A Wang Hao-juan
%A Qin Hao-yang
%A Ning Ning
%A Yang Mo-hua
%A <br>吴霜毅
%A 于奇
%A 王浩娟
%A 覃浩洋
%A 宁宁
%A 杨谟华
%J 电子与信息学报
%D 2007
%I 
%X Based on multi-stage comparison, a new theory incorporating Minimum Comparator Number Algorithm (MCNA) and Power-Conversion Rate Merit Model (PCRMM) is proposed, which releases the power dissipation from limitation of comparators, sub-DACs and residual amplifiers in high-speed high-resolution ADCs. Under 10-bit ADC resolution specific, theoretical analysis shows that this theory reduces the power dissipation of Flash ADC to minimum by applying 3-stage Pipelined ADC, while keeping ADC high-speed, and it also proves that two-step ADC is better than other type of multi-step ADC. This new theory can be used in designing and developing high-speed low-power ADCs.
%K Power-Conversion Rate Merit Model (PCRMM)
%K ADC
%K Comparator
%K Low-power<br>功耗-速率优值模型
%K 模数转换器
%K 比较器
%K 低功耗
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=EFC0377B03BD8D0EF4BBB548AC5F739A&aid=B1D516AD8CBF1B2A&yid=A732AF04DDA03BB3&vid=771469D9D58C34FF&iid=5D311CA918CA9A03&sid=37904DC365DD7266&eid=67289AFF6305E306&journal_id=1009-5896&journal_name=电子与信息学报&referenced_num=0&reference_num=4