A REAL-TIME 2-D DCT/IDCT PROCESSOR USING FPGAs
基于FPGA和2位串行分布式算法的实时高速二维DCT/IDCT处理器研制

Based on the skew-circular convolution distributed algorithm presented by W.Li(1991). A 8×8 2-D DCT/IDCT processor has been designed using FPGAs, which can be used for HDTV s decoder or other signal and information processing systems. It can be used to calculate either DCT or IDCT depending on a single control line. AM of the input/output are 12-bit and the internal data bus and internal parameters are 16-bit.