%0 Journal Article
%T A REAL-TIME 2-D DCT/IDCT PROCESSOR USING FPGAs<br>基于FPGA和2位串行分布式算法的实时高速二维DCT/IDCT处理器研制
%A Xiang Hui
%A Teng Jianfu
%A Wang Chengning
%A <br>向晖
%A 滕建辅
%A 王承宁
%J 电子与信息学报
%D 1999
%I 
%X Based on the skew-circular convolution distributed algorithm presented by W.Li(1991). A 8×8 2-D DCT/IDCT processor has been designed using FPGAs, which can be used for HDTV s decoder or other signal and information processing systems. It can be used to calculate either DCT or IDCT depending on a single control line. AM of the input/output are 12-bit and the internal data bus and internal parameters are 16-bit.
%K FPGA(Field Programmable Gate Arry)
%K 2-D DCT/IDCT processor
%K Distributed algorithm<br>现场可编程门阵列
%K 二维DCT/IDCT处理器
%K 分布式算法
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=EFC0377B03BD8D0EF4BBB548AC5F739A&aid=2C273403315A260ADA3EBFD607012D71&yid=B914830F5B1D1078&vid=659D3B06EBF534A7&iid=B31275AF3241DB2D&sid=97747634025A5F36&eid=8C8D39B86A1EED4F&journal_id=1009-5896&journal_name=电子与信息学报&referenced_num=0&reference_num=4