A 10bit 50MS/s Pipeline ADC Design for a Million Pixels Level CMOS Image Sensor
用于百万像素级CMOS图像传感器的10位50MS/s流水线ADC设计

High speed and high accuracy ADC is a necessary part in large pixel scale CMOS image sensor. As evolution of technology, low power consumption design has attracted a lot attention. To reduce power consumption without losing performance, the same structure amplifiers are biased with the same bias circuit, and adopt cascode compensation to reduce power consumption. Noise and mismatch are more important error sources in pipeline ADC, so careful calculation and system simulation have been carried out by using Matlab in this paper. In this paper, a 10 bit 50MS/s pipeline ADC core has been presented, which can be used in large pixel scale CMOS image sensor. A balance between performance and power consumption has been achieved.