A Low Jitter PLL in a 90nm CMOS Digital Process
用90nm CMOS数字工艺实现的低抖动时钟锁相环设计

A low jitter phase-locked loop (PLL) that does not need analog resistors and capacitors is designed and fabricated in a 90nm CMOS digital process.The metal parasitic capacitor is used in the PLL loop filter.Test results show that when the PLL is locked on 1.989GHz,the RMS jitter is 3.7977ps,the peak-to-peak jitter is 31.225ps,and the power consumption is about 9mW.The locked output frequency range is from 125MHz to 2.7GHz.