%0 Journal Article
%T A Low Jitter PLL in a 90nm CMOS Digital Process<br>用90nm CMOS数字工艺实现的低抖动时钟锁相环设计
%A Yin Haifeng
%A Wang Feng
%A Liu Jun
%A Mao Zhigang
%A <br>尹海丰
%A 王峰
%A 刘军
%A 毛志刚
%J 半导体学报
%D 2008
%I 
%X A low jitter phase-locked loop (PLL) that does not need analog resistors and capacitors is designed and fabricated in a 90nm CMOS digital process.The metal parasitic capacitor is used in the PLL loop filter.Test results show that when the PLL is locked on 1.989GHz,the RMS jitter is 3.7977ps,the peak-to-peak jitter is 31.225ps,and the power consumption is about 9mW.The locked output frequency range is from 125MHz to 2.7GHz.
%K PLL
%K PFD
%K charge pump
%K VCO<br>锁相环
%K 鉴频鉴相器
%K 电荷泵
%K 压控振荡器EEACC:2570
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=025C8057C4D37C4BA0041DC7DE7C758F&aid=04729956C0522797011C6022AB3294B1&yid=67289AFF6305E306&vid=771469D9D58C34FF&iid=5D311CA918CA9A03&sid=3DB657DD5E356007&eid=CA590345B99F3387&journal_id=1674-4926&journal_name=半导体学报&referenced_num=0&reference_num=7