Delay and Energy Efficient Design of an On-Chip Bus with Repeaters Using a New Spatial and Temporal Encoding Technique
基于一种新的时空编码技术的片上总线的低延迟低能耗设计

On-chip global buses in deep sub-micron designs consume significant amounts of energy and have large propagation delays.Thus,minimizing energy dissipation and propagation delay is an important design objective.In this paper,we propose a new spatial and temporal encoding approach for generic on-chip global buses with repeaters that enables higher performance while reducing peak energy and average energy.The proposed encoding approach exploits the benefits of a temporal encoding circuit and spatial bus-invert coding techniques to simultaneously eliminate opposite transitions on adjacent wires and reduce the number of self-transitions and coupling-transitions.In the design process of applying encoding techniques for reduced bus delay and energy,we present a repeater insertion design methodology to determine the repeater size and inter-repeater bus length,which minimizes the total bus energy dissipation while satisfying target delay and slew-rate constraints.This methodology is employed to obtain optimal energy versus delay trade-offs under slew-rate constraints for various encoding techniques.