%0 Journal Article
%T Delay and Energy Efficient Design of an On-Chip Bus with Repeaters Using a New Spatial and Temporal Encoding Technique<br>基于一种新的时空编码技术的片上总线的低延迟低能耗设计
%A Zhang Qingli
%A Wang Jinxiang
%A Yu Mingyan
%A Ye Yizheng
%A <br>张庆利
%A 王进祥
%A 喻明艳
%A 叶以正
%J 半导体学报
%D 2008
%I 
%X On-chip global buses in deep sub-micron designs consume significant amounts of energy and have large propagation delays.Thus,minimizing energy dissipation and propagation delay is an important design objective.In this paper,we propose a new spatial and temporal encoding approach for generic on-chip global buses with repeaters that enables higher performance while reducing peak energy and average energy.The proposed encoding approach exploits the benefits of a temporal encoding circuit and spatial bus-invert coding techniques to simultaneously eliminate opposite transitions on adjacent wires and reduce the number of self-transitions and coupling-transitions.In the design process of applying encoding techniques for reduced bus delay and energy,we present a repeater insertion design methodology to determine the repeater size and inter-repeater bus length,which minimizes the total bus energy dissipation while satisfying target delay and slew-rate constraints.This methodology is employed to obtain optimal energy versus delay trade-offs under slew-rate constraints for various encoding techniques.
%K on-chip buses
%K delay
%K energy
%K encoding
%K repeaters<br>片上总线
%K 延时
%K 能量有效
%K 编码
%K 中继驱动器
%K on-chip
%K buses
%K delay
%K energy
%K encoding
%K repeaters
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=025C8057C4D37C4BA0041DC7DE7C758F&aid=A901691ACCD5B4B8A83F3109571B69C9&yid=67289AFF6305E306&vid=771469D9D58C34FF&iid=E158A972A605785F&sid=94655B9881133A28&eid=20D29EF591CB2C94&journal_id=1674-4926&journal_name=半导体学报&referenced_num=0&reference_num=16