Design of Low Power and High Performance Explicit-Pulsed Flip-Flops
新型高速低功耗显式脉冲触发器电路设计

The speed and delay of flip-flops are critical to the performance of digital circuit systems.Two novel structures for dual-edge triggered explicit-pulsed flip-flops are proposed in this paper.The charging and discharging times are greatly reduced due to the lower capacitance of the interval nodes in the new structures,and the short circuit power consumption is diminished by overcoming the race problem as well.The flip-flops are also superior to the structures reported in the literature in terms of both power dissipation and working speed.