A 10 Gb/s burst-mode clock and data recovery circuit
10Gb/s突发模式时钟数据恢复电路设计

The burst-mode clock and data recovery is one of the key technologies of the 10-Gigabit Ethernet Passive Optical Networks (10G-EPON) system. In this paper, we introduced a gated oscillator based on XONR/XOR cells and illustrated its working process. A half-rate BM-CDR circuit based on the proposed oscillator is designed. The design is implemented in SMIC 0.13?m CMOS technology, occupying an area of 675?m ? 625?m. The measured results show that this circuit can recover out burst-mode clock and data which meet the IEEE standard 802.3av definitions for 10Gbit/s burst-mode data transfer, the locking time is less than 5 bits.