%0 Journal Article
%T A 10 Gb/s burst-mode clock and data recovery circuit<br>10Gb/s突发模式时钟数据恢复电路设计
%A Gu Gaowei
%A Zhu En
%A Lin Ye
%A Liu Wensong
%A <br>顾皋蔚
%A 朱恩
%A 林叶
%A 刘文松
%J 半导体学报
%D 2012
%I 
%X The burst-mode clock and data recovery is one of the key technologies of the 10-Gigabit Ethernet Passive Optical Networks (10G-EPON) system. In this paper, we introduced a gated oscillator based on XONR/XOR cells and illustrated its working process. A half-rate BM-CDR circuit based on the proposed oscillator is designed. The design is implemented in SMIC 0.13?m CMOS technology, occupying an area of 675?m ? 625?m. The measured results show that this circuit can recover out burst-mode clock and data which meet the IEEE standard 802.3av definitions for 10Gbit/s burst-mode data transfer, the locking time is less than 5 bits.
%K 10Gigabit Ethernet passive optical networks (10G-EPON)
%K Clock and data recovery(CDR)
%K burst-mode (BM)
%K gated voltage-controlled-oscillator (GVCO)
%K Frequency locked loop (FLL)<br>数据恢复电路
%K 突发模式
%K 时钟
%K Gb
%K CMOS技术
%K IEEE标准
%K 电路设计
%K 振荡器
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=025C8057C4D37C4BA0041DC7DE7C758F&aid=6054DFDC987AA8B2ACD73DC876CCC166&yid=99E9153A83D4CB11&vid=27746BCEEE58E9DC&iid=DF92D298D3FF1E6E&sid=A415EFE2496BAD93&eid=94C357A881DFC066&journal_id=1674-4926&journal_name=半导体学报&referenced_num=0&reference_num=10