A PVT Tolerant Sub-mA PLL for High Speed Links
一个用于高速信号传输的对PVT变化不敏感的低功耗锁相环

A sub-mA phase-locked loop fabricated in a 65nm standard digital CMOS process is presented.The impact of process variation is largely removed by a novel open-loop calibration that is performed only during start-up but is opened during normal operation.This method reduces calibration time significantly compared with its closed-loop counterpart.The dual-loop PLL architecture is adopted to achieve a process-independent damping factor and pole-zero separation.A new phase frequency detector embedded with a level shifter is introduced.Careful power partitioning is explored to minimize the noise coupling.The proposed PLL achieves 3.1ps RMS jitter running at 1.6GHz while consuming only 0.94mA.