%0 Journal Article
%T A PVT Tolerant Sub-mA PLL for High Speed Links<br>一个用于高速信号传输的对PVT变化不敏感的低功耗锁相环
%A Yang Yi
%A Yang Liqiong
%A Zhang Feng
%A Gao Zhuo
%A Huang Lingyi
%A Hu Weiwu
%A <br>杨祎
%A 杨丽琼
%A 张锋
%A 高茁
%A 黄令仪
%A 胡伟武
%J 半导体学报
%D 2008
%I 
%X A sub-mA phase-locked loop fabricated in a 65nm standard digital CMOS process is presented.The impact of process variation is largely removed by a novel open-loop calibration that is performed only during start-up but is opened during normal operation.This method reduces calibration time significantly compared with its closed-loop counterpart.The dual-loop PLL architecture is adopted to achieve a process-independent damping factor and pole-zero separation.A new phase frequency detector embedded with a level shifter is introduced.Careful power partitioning is explored to minimize the noise coupling.The proposed PLL achieves 3.1ps RMS jitter running at 1.6GHz while consuming only 0.94mA.
%K PLL
%K PVT variation
%K jitter<br>锁相环
%K PVT变化
%K 抖动
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=025C8057C4D37C4BA0041DC7DE7C758F&aid=3F76BFCAB879D9950432B3EAACCE6396&yid=67289AFF6305E306&vid=771469D9D58C34FF&iid=F3090AE9B60B7ED1&sid=8F23BB34AC8262BD&eid=AF251ABCE889FAF8&journal_id=1674-4926&journal_name=半导体学报&referenced_num=2&reference_num=13