Reducing Leakage of SRAM Using Dual-Gate-Oxide-Thickness Transistors in 45nm Bulk Technology
45nm体硅工艺下使用双-栅氧化层厚度降低SRAM的泄漏功耗

This paper presents a method based on dual-gate-oxide-thickness assignment to reduce the total leakage power dissipation of SRAM in 45nm bulk technology.The proposed technique incurs neither area nor delay overhead and can improve the static noise margin.In addition,it results in a slight change in the SRAM design flow.Three novel SRAM cell configurations are proposed.Simulation results demonstrate that this technique can reduce the total leakage power dissipation of 32kb of SRAM with these configurations by more than 50%.