%0 Journal Article
%T Reducing Leakage of SRAM Using Dual-Gate-Oxide-Thickness Transistors in 45nm Bulk Technology<br>45nm体硅工艺下使用双-栅氧化层厚度降低SRAM的泄漏功耗
%A Yang Song
%A Wang Hong
%A Yang Zhijia
%A <br>杨松
%A 王宏
%A 杨志家
%J 半导体学报
%D 2007
%I 
%X This paper presents a method based on dual-gate-oxide-thickness assignment to reduce the total leakage power dissipation of SRAM in 45nm bulk technology.The proposed technique incurs neither area nor delay overhead and can improve the static noise margin.In addition,it results in a slight change in the SRAM design flow.Three novel SRAM cell configurations are proposed.Simulation results demonstrate that this technique can reduce the total leakage power dissipation of 32kb of SRAM with these configurations by more than 50%.
%K gate leakage current
%K SRAM
%K gate-oxide-thickness
%K SNM<br>栅极泄漏电流
%K SRAM
%K 栅氧化层厚度
%K 静态噪声边界
%K 体硅工艺
%K 使用
%K 栅氧化层厚度
%K SRAM
%K 泄漏功耗
%K Technology
%K Bulk
%K Transistors
%K 仿真结果
%K 单元设计
%K 单元结构
%K 改动
%K 设计流程
%K 边界
%K 噪声
%K 改善
%K 延时
%K 面积
%K 方法
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=025C8057C4D37C4BA0041DC7DE7C758F&aid=DF0C380C13248DF0&yid=A732AF04DDA03BB3&vid=D3E34374A0D77D7F&iid=94C357A881DFC066&sid=04EA291949415E08&eid=762CFFBBDED11937&journal_id=1674-4926&journal_name=半导体学报&referenced_num=0&reference_num=9