High-Speed CMOS Sample-and-Hold Amplifier
High-Speed CMOS Sample- and-Hold Amplifier

A newly designed sample-and-hold(S/H) integrated circuit based on the 1.5 micr on N-w ell CMOS technology for 8-bit high-speed analog to digital converter is descri be d. It can realize the 40-MHz sampling rate and 8-bit resolution. The good perf or mance of S/H circuit benefits from the use of a newly designed regulated cascod e operator amplifier, which has a DC gain of 140-dB, unity-gain bandwidth of 407-MHz, phase margin of 53 degree and power consumption of 90mW. It is superi or to the operator amplifier of 60\|dB, 107\|MHz, 13 degree, and 33mW respective ly, which is used in the similar S/H circuit based on the 0.8 micron technology and designed by Michio Yotsuyanagi.