%0 Journal Article
%T High-Speed CMOS Sample-and-Hold Amplifier<br>High-Speed CMOS Sample- and-Hold Amplifier
%A WU Ge
%A SHI Yin
%A <br>兀革
%A 石寅
%J 半导体学报
%D 2000
%I 
%X A newly designed sample-and-hold(S/H) integrated circuit based on the 1.5 micr on N-w ell CMOS technology for 8-bit high-speed analog to digital converter is descri be d. It can realize the 40-MHz sampling rate and 8-bit resolution. The good perf or mance of S/H circuit benefits from the use of a newly designed regulated cascod e operator amplifier, which has a DC gain of 140-dB, unity-gain bandwidth of 407-MHz, phase margin of 53 degree and power consumption of 90mW. It is superi or to the operator amplifier of 60\|dB, 107\|MHz, 13 degree, and 33mW respective ly, which is used in the similar S/H circuit based on the 0.8 micron technology and designed by Michio Yotsuyanagi.
%K CMOS
%K amplifier
%K converter<br>放大器
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=025C8057C4D37C4BA0041DC7DE7C758F&aid=7822EE12203F8B18&yid=9806D0D4EAA9BED3&vid=659D3B06EBF534A7&iid=9CF7A0430CBB2DFD&sid=85C7135C065B9251&eid=51E4ADE955550A0C&journal_id=1674-4926&journal_name=半导体学报&referenced_num=0&reference_num=6