Computation Model and Realization Method of IC Critical Area Based on Etching Process
基于刻蚀工艺的IC关键面积计算模型与实现方法

Over etching or under etching in IC process causes the variation of the linewidth and spacing between two parallel lines because of the random disturbance of the process.The influence on over etching and under etching to IC layout is analyzed,the computation model and realization method of IC critical area are presented.The simulation result is in agreement with the theoretical analysis.