%0 Journal Article
%T Computation Model and Realization Method of IC Critical Area Based on Etching Process<br>基于刻蚀工艺的IC关键面积计算模型与实现方法
%A Zhao Tianxu
%A Hao Yue
%A Ma Peijun
%A <br>赵天绪
%A 郝跃
%A 马佩军
%J 半导体学报
%D 2002
%I 
%X Over etching or under etching in IC process causes the variation of the linewidth and spacing between two parallel lines because of the random disturbance of the process.The influence on over etching and under etching to IC layout is analyzed,the computation model and realization method of IC critical area are presented.The simulation result is in agreement with the theoretical analysis.
%K critical area
%K random disturbance
%K defect<br>关键面积
%K 随机扰动
%K 缺陷
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=025C8057C4D37C4BA0041DC7DE7C758F&aid=4D924566C291CDAD&yid=C3ACC247184A22C1&vid=EA389574707BDED3&iid=CA4FD0336C81A37A&sid=331211A5F5616413&eid=F24949CFDB502409&journal_id=1674-4926&journal_name=半导体学报&referenced_num=0&reference_num=2