The Jitter Performance Comparison Between DLL and PLL-Based RF CMOS Oscillators
对基于DLL和PLL的射频CMOS振荡器的相位抖动比较(英文)

By jitter performance comparison between PLL (Phase Locked Loop) and DLL (Delay Locked Loop),a helpful equation is derived for the structure choice between DLL and PLL based synthesizers fabricated in CMOS processes to get an optimum jitter performance and power consumption.For a frequency synthesizer,a large multiple factor prefers PLL based configuration which consumes less power,while a small one needs DLL based topology which produces a better jitter performance.