%0 Journal Article
%T The Jitter Performance Comparison Between DLL and PLL-Based RF CMOS Oscillators<br>对基于DLL和PLL的射频CMOS振荡器的相位抖动比较(英文)
%A Li Jincheng
%A Qiu Yulin
%A <br>李金城
%A 仇玉林
%J 半导体学报
%D 2001
%I 
%X By jitter performance comparison between PLL (Phase Locked Loop) and DLL (Delay Locked Loop),a helpful equation is derived for the structure choice between DLL and PLL based synthesizers fabricated in CMOS processes to get an optimum jitter performance and power consumption.For a frequency synthesizer,a large multiple factor prefers PLL based configuration which consumes less power,while a small one needs DLL based topology which produces a better jitter performance.
%K Jitter
%K PLL
%K DLL
%K frequency synthesizer
%K RF CMOS transceiver
%K Local Oscillator(LO)
%K Voltage Controlled Delay Line(VCDL)
%K VCO<br>相位抖动
%K PLL
%K 延时锁相环
%K 频率合成器
%K 射频CMOS收发器
%K 本振
%K 压控延时线
%K 压控振荡器
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=025C8057C4D37C4BA0041DC7DE7C758F&aid=EDC0233DBA477A81&yid=14E7EF987E4155E6&vid=BC12EA701C895178&iid=F3090AE9B60B7ED1&sid=9D6E80F951A5107A&eid=0522AC581E488FBF&journal_id=1674-4926&journal_name=半导体学报&referenced_num=0&reference_num=5