A Low-Latency Low-Power Scheme for On-Chip Global Interconnects
一种低延迟低功耗的片上全局互连方法

A hybrid insertion scheme for on-chip global interconnects is presented.The scheme takes advantages of repeaters and low-swing differential-signaling circuits on driving long wires in different length,and optimally inserts them along the wire in order to decrease delay and power of interconnects.It is shown that the delay,energy,delay-energy-product,and area are all considerably decreased compared with other available schemes.