%0 Journal Article
%T A Low-Latency Low-Power Scheme for On-Chip Global Interconnects<br>一种低延迟低功耗的片上全局互连方法
%A Liu Xiangyuan
%A Chen Shuming
%A <br>刘祥远
%A 陈书明
%J 半导体学报
%D 2005
%I 
%X A hybrid insertion scheme for on-chip global interconnects is presented.The scheme takes advantages of repeaters and low-swing differential-signaling circuits on driving long wires in different length,and optimally inserts them along the wire in order to decrease delay and power of interconnects.It is shown that the delay,energy,delay-energy-product,and area are all considerably decreased compared with other available schemes.
%K on-chip interconnect
%K delay
%K energy
%K area
%K low-swing
%K differential-signaling<br>片上互连
%K 延时
%K 能耗
%K 面积
%K 低摆幅
%K 差分信号
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=025C8057C4D37C4BA0041DC7DE7C758F&aid=3F69339D0D1EA9C3&yid=2DD7160C83D0ACED&vid=96C778EE049EE47D&iid=9CF7A0430CBB2DFD&sid=0ADDA70032243493&eid=A477487C019ACAC8&journal_id=1674-4926&journal_name=半导体学报&referenced_num=0&reference_num=16