Performance Modeling and Architecture Optimization of Synthesizable Arithmetic Circuits
可综合算术运算单元的性能建模及VLSI结构优化

A performance evaluation and modeling method for synthesizable arithmetic circuit is proposed.Based on the unit gate model,it is feasible to estimate the delay and area of arithmetic circuits at the beginning of design period,therefore the design iteration is avoided.The effectiveness is proved by the applications of the proposed method to various binary adders.