%0 Journal Article
%T Performance Modeling and Architecture Optimization of Synthesizable Arithmetic Circuits<br>可综合算术运算单元的性能建模及VLSI结构优化
%A Shen Bo
%A Zhang Qianling
%A <br>沈泊
%A 章倩苓
%J 半导体学报
%D 2002
%I 
%X A performance evaluation and modeling method for synthesizable arithmetic circuit is proposed.Based on the unit gate model,it is feasible to estimate the delay and area of arithmetic circuits at the beginning of design period,therefore the design iteration is avoided.The effectiveness is proved by the applications of the proposed method to various binary adders.
%K unit
%K gate model
%K performance evaluation
%K binary adders<br>单位门模型
%K 性能评估
%K 加法器
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=025C8057C4D37C4BA0041DC7DE7C758F&aid=49045FAF9E74DF14&yid=C3ACC247184A22C1&vid=EA389574707BDED3&iid=59906B3B2830C2C5&sid=81ED2BA99A995222&eid=530D9656D932F420&journal_id=1674-4926&journal_name=半导体学报&referenced_num=0&reference_num=12