A Regular Time-Efficient VLSI Architecture for Multiplication Modulo 2n＋1
一种规整高速的费马数模乘的VLSI结构

A VLSI architecture is described based on MCSA (Modular Carried Saved Adder) for multiplication modulo a Fermat Prime. The theoretic analysis and the result from synthesis and simulation show that it makes a good trade\|off between speed and area.This modular multiplication makes the IDEA(International Data Encrypt Algorithm) more efficient.