%0 Journal Article
%T A Regular Time-Efficient VLSI Architecture for Multiplication Modulo 2n＋1<br>一种规整高速的费马数模乘的VLSI结构
%A ZHOU Hao
%A |hua
%A LI Zhi
%A |yong
%A XIE Wen
%A |lu
%A ZHANG Qian
%A |ling
%A <br>周浩华
%A 李志勇
%A 谢文录
%A 章倩苓
%J 半导体学报
%D 2000
%I 
%X A VLSI architecture is described based on MCSA (Modular Carried Saved Adder) for multiplication modulo a Fermat Prime. The theoretic analysis and the result from synthesis and simulation show that it makes a good trade\|off between speed and area.This modular multiplication makes the IDEA(International Data Encrypt Algorithm) more efficient.
%K multiplication
%K VLSI architecture<br>模乘
%K VLSI结构
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=025C8057C4D37C4BA0041DC7DE7C758F&aid=0765DCF1900BA523&yid=9806D0D4EAA9BED3&vid=659D3B06EBF534A7&iid=F3090AE9B60B7ED1&sid=31CCC5D591A72A74&eid=1F51A4E3D1D75885&journal_id=1674-4926&journal_name=半导体学报&referenced_num=4&reference_num=9