Researches on the high-speed divider in the PLL frequency synthesizer
锁相环型频率综合器中高速分频器的研究

In this paper, the design of the high-speed divider in the PLL frequency synthesizer is investigated. The characteristics of circuits concerning speed and power are compared between the synchronous divider and the asynchronous divider. Considering the different demands for the divide-by-2 circuits in the phase-switching asynchronous divider, several different circuits topology of the divide-by-2 circuits are presented. And the charge sharing problem of the divide-by-2 circuit in a reference paper is solved in this paper. According to the simulation results, the highest working frequency of the first and the improved second divider-by-2 circuits is 3.3GHz, and the current consumption is 1.9mA.