%0 Journal Article
%T Researches on the high-speed divider in the PLL frequency synthesizer<br>锁相环型频率综合器中高速分频器的研究
%A YUAN Quan
%A YANG Hai-Gang
%A DONG Fang-Yuan
%A YIN Tao
%A <br>袁泉
%A 杨海钢
%A 董方源
%A 尹韬
%J 中国科学院研究生院学报
%D 2008
%I 
%X In this paper, the design of the high-speed divider in the PLL frequency synthesizer is investigated. The characteristics of circuits concerning speed and power are compared between the synchronous divider and the asynchronous divider. Considering the different demands for the divide-by-2 circuits in the phase-switching asynchronous divider, several different circuits topology of the divide-by-2 circuits are presented. And the charge sharing problem of the divide-by-2 circuit in a reference paper is solved in this paper. According to the simulation results, the highest working frequency of the first and the improved second divider-by-2 circuits is 3.3GHz, and the current consumption is 1.9mA.
%K phase-locked loop
%K asynchronous divider
%K synchronous divider
%K charge sharing<br>锁相环
%K 异步分频器
%K 同步分频器
%K 电荷分享
%K 锁相
%K 环型
%K 频率综合器
%K 分频器
%K frequency
%K synthesizer
%K 消耗
%K 电流
%K 最高工作频率
%K 工艺
%K CMOS
%K 有效解决
%K 分频电路
%K 仿真显示
%K 改进
%K 问题
%K 电荷分享
%K 存在
%K Wang
%K 方案
%K 切换型
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=B5EDD921F3D863E289B22F36E70174A7007B5F5E43D63598017D41BB67247657&cid=B47B31F6349F979B&jid=67CDFDECD959936E166E0F72DE972847&aid=39A628532025610447C3918F51F2B51C&yid=67289AFF6305E306&vid=C5154311167311FE&iid=E158A972A605785F&sid=811ACA5D3673A764&eid=4AB4178709047BE3&journal_id=1002-1175&journal_name=中国科学院研究生院学报&referenced_num=0&reference_num=7