Implementation of radar monitoring and controlling system based on the SOPC of NiosII CPU
基于NiosII片上可编程系统(SOPC)实现的雷达监控系统

This study presents a radar monitoring and controlling system which is mainly based on the NiosII CPU and introduces the hardware integration and software design flow of the system on programmable chip. The kernel of design is Cyclone II family FPGA which supports the 32 bits high performance NiosII CPU, and application software is developed in NiosII IDE environment tool. Compared with the traditional monitoring and controlling system, the present design has capabilities of fast data transmitting, low power consumming, and high integration.