Numerical Study on a Lateral Double-Gate Tunnelling Field Effect Transistor

A novel lateral double-gate tunnelling field effect transistor (DG-TFET) is studied and its performance is presented by a two-dimensional device simulation with code ISE. The result demonstrates that this new tunnelling transistor allows for the steeper sub-threshold swing below 60 mV/dec, the super low supply voltage (operable at VDD<0.3 V) and the rail-to-rail logic (significant on-state current at the drain-source voltage VDS=50 mV) for the aggressive technology assumptions of the availability of high-k/metal stack with equivalent gate oxide thickness EOT=0.24 nm and the work function difference 4.5 eV of materials.