Characterization of on-chip balun with patterned floating shield in 65 nm CMOS
65-nm CMOS上带图案悬浮屏蔽的片上巴伦的特性

A simple method of balun synthesis is proposed to estimate the balun structure in the operating frequency band. Then, a careful optimization is implemented to evaluate the estimated structure by a series of EM simulations. In order to investigate the impact of the patterned floating shield (PFS), the optimized baluns with and without PFS are fabricated in a 65 nm 1P6M CMOS process. The measurement results demonstrate that the PFS obviously improves the insertion loss (IL) in the frequency range and a linear improving trend appears smoothly. It is also found that the PFS gradually improves the phase balance as the frequency increases, while it has a very slight influence on the magnitude balance. To characterize the device's intrinsic power transfer ability, we propose a method to obtain the baluns' maximum available gain directly from the measured 3-port S-parameters and find that IL-comparison may not be very objective when evaluating the shielding effect. We also use the resistive coupling efficiency to characterize the shielding effect, and an imbalanced shielding efficiency is found though the PFS is perfectly symmetric in the measurement. It can be demonstrated that this phenomenon comes from the intrinsic imbalance of our balun layout.