Design of an Ultra Low Power Clock Gating D Flip-Flop Using Quasi-Static Energy Recovery Logic

This paper presents low power clock gating adiabatic D flip-flop using single phase sinusoidal power clock scheme. We propose the clock gated single phase Quasi-Static Energy Recovery Logic (QSERL) D flip-flop at 90nm CMOS technology. In the previously proposed QSERL logic, two phase sinusoidal power clocks were used that increased the hardware complexity and clocking issues. In this paper, single phase QSERL is proposed to reduce the hardware complexity and clocking issues. The clock gating technique is applied to a QSERL D flip-flop during idle periods of clock. The proposed scheme works efficiently with reduced power loss. All the simulations have been performed using Cadence spectre simulator.