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Design & Analysis of 5 nm PDSOI and FDSOI n-MOSFETs for Ultra-Low Power Applications with High-k Dielectric Materials

DOI: 10.4236/msa.2026.172003, PP. 35-49

Keywords: PDSOI, FDSOI, 5 nm Node, High-k Gate Dielectric, n-MOSFET

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Abstract:

In this study, a comparison of 5 nm PDSOI and FDSOI n-MOSFETs with SiO2 and high-k gate dielectrics is carried out using Silvaco TCAD ATLAS platform with necessary models. SOI architectures (PDSOI/FDSOI) offer enhanced electrostatic control compared to bulk CMOS, which suffers from threshold instability, SCEs and leakage near the 20 nm node. In this scaling, various high-k dielectric materials were explored for gate oxide. Among those, Ta2O5 shows comparatively much better results with respect to the optimized SiO2-gated device of the same SOI architecture. The PDSOI device showed 39.15% lower Threshold Voltage (Vth), 26.5% improved Subthreshold-Swing (SS), leakage current (IOFF) of 2.17 × 10？10 A, and ION/IOFF ratio of 1.64 × 106, making it suitable for analog and near-threshold logic applications. The FDSOI device exhibited closely unchanged Vth of 0.6604 V, 34% improved SS, ultra-low IOFF of 1.69 × 10？13 A and ION/IOFF ratio 7.41 × 109 favoring use in high-speed and ultra-low-leakage digital systems. This paper gives valuable insight and guidelines for selecting optimal SOI architectures and gate dielectric materials in future ultra-scaled, energy-efficient, and high-performance integrated circuits.

 References

[1]  Frank, D.J., Dennard, R.H., Nowak, E., Solomon, P.M., Taur, Y. and Wong, H.S.P. (2001) Device Scaling Limits of Si MOSFETs and Their Application Dependencies. Proceedings of the IEEE, 89, 259-288.
https://doi.org/10.1109/5.915374
[2]  Bondyopadhyay, P.K. (1998) Moore’s Law Governs the Silicon Revolution. Proceedings of the IEEE, 86, 78-81.
https://doi.org/10.1109/5.658761
[3]  Vashishtha, V. and Clark, L.T. (2021) Comparing Bulk-Si FinFET and Gate-All-Around FETs for the 5nm Technology Node. Microelectronics Journal, 107, Article ID: 104942.
https://doi.org/10.1016/j.mejo.2020.104942
[4]  Chowdhury, T.A. (2023) Simulation Study of 50nm Gate Length MOSFET Characteristics. Advances in Materials Physics and Chemistry, 13, 121-134.
https://doi.org/10.4236/ampc.2023.136009
[5]  Vora, P.H. and Lad, R. (2017) A Review Paper on CMOS, SOI and FinFET Technology. Design and Reuse Industry Articles, 1-10
https://www.design-reuse.com/article/60939-a-review-paper-on-cmos-soi-and-finfet-technology/
[6]  Cristoloveanu, S. (2001) Silicon on Insulator Technologies and Devices: From Present to Future. Solid-State Electronics, 45, 1403-1411.
https://doi.org/10.1016/s0038-1101(00)00271-9
[7]  Shashwat, Singh, A.K., Misra, R., Wadhwa, G., Nirosha, R. and Agarwal, R. (2022) Design and Performance Analysis of Partially Depleted and Fully Depleted Silicon on Insulator MOSFET. Journal of Physics: Conference Series, 2335, Article ID: 012042.
https://doi.org/10.1088/1742-6596/2335/1/012042
[8]  Chowdhury, T.A. (2023) Simulation Study of Nanoscale FDSOI MOSFET Characteristics. Soft Nanoscience Letters, 13, 13-22.
https://doi.org/10.4236/snl.2023.133002
[9]  Ren, J.Z. and Salama, C.A.T. (2000) 1 V SOI NMOSFET with Suppressed Floating Body Effects. Solid-State Electronics, 44, 1931-1937.
https://doi.org/10.1016/s0038-1101(00)00167-2
[10]  Lederer, D., Flandre, D. and Raskin, J. (2004) AC Behavior of Gate-Induced Floating Body Effects in Ultrathin Oxide PD SOI MOSFETs. IEEE Electron Device Letters, 25, 104-106.
https://doi.org/10.1109/led.2003.822658
[11]  Wei, H.W. and Ruslan, S.H. (2019) Investigation of FDSOI and PDSOI MOSFET Characteristics. AIP Conference Proceedings, 2173, Article ID: 020005.
https://doi.org/10.1063/1.5133920
[12]  Colinge, J.P. (2004) Silicon-On-Insulator Technology: Materials to VLSI. Springer eBooks.
[13]  Orouji, A.A. and Abbasi, A. (2012) Novel Partially Depleted SOI MOSFET for Suppression Floating-Body Effect: An Embedded JFET Structure. Superlattices and Microstructures, 52, 552-559.
https://doi.org/10.1016/j.spmi.2012.06.006
[14]  Vitale, S.A., Wyatt, P.W., Checka, N., Kedzierski, J. and Keast, C.L. (2011) FDSOI Process Technology for Subthreshold-Operation Ultra-Low-Power Electronics. ECS Transactions, 35, 179-188.
https://doi.org/10.1149/1.3570794
[15]  Radamson, H.H., Miao, Y., Zhou, Z., Wu, Z., Kong, Z., Gao, J., et al. (2024) CMOS Scaling for the 5nm Node and Beyond: Device, Process and Technology. Nanomaterials, 14, Article 837.
https://doi.org/10.3390/nano14100837
[16]  Rao, M.V.G., Ramanjaneyulu, N., Pydi, B., Soma, U., Babu, K.R. and Prasad, S.H. (2023) Enhancing Performance of Dual-Gate FinFET with High-K Gate Dielectric Materials in 5nm Technology: A Simulation Study. Transactions on Electrical and Electronic Materials, 24, 557-569.
https://doi.org/10.1007/s42341-023-00473-5
[17]  Radamson, H.H., He, X., Zhang, Q., Liu, J., Cui, H., Xiang, J., et al. (2019) Miniaturization of CMOs. Micromachines, 10, Article 293.
https://doi.org/10.3390/mi10050293
[18]  Chaudhry, A. and Kumar, M.J. (2004) Controlling Short-Channel Effects in Deep-Submicron SOI MOSFETs for Improved Reliability: A Review. IEEE Transactions on Device and Materials Reliability, 4, 99-109.
https://doi.org/10.1109/tdmr.2004.824359
[19]  Abo, S., Mizutani, M., Ikeda, K., Kinomura, A., Iwamatsu, T., Maegawa, S., et al. (2003) Investigation of Floating Body Effects in PD-SOI-MOSFET Using Proton Microprobe. Nuclear Instruments and Methods in Physics Research Section B: Beam Interactions with Materials and Atoms, 210, 216-220.
https://doi.org/10.1016/s0168-583x(03)01009-7
[20]  Manual, ATLAS User’s (2004) Manual Device Simulation Software, Santa Clara, Calif.
https://www.eng.buffalo.edu/~wie/silvaco/atlas_user_manual.pdf
[21]  Vimala, P. and Balamurugan, N.B. (2012) Quantum Mechanical Compact Modeling of Symmetric Double-Gate MOSFETs Using Variational Approach. Journal of Semiconductors, 33, Article ID: 034001.
https://doi.org/10.1088/1674-4926/33/3/034001
[22]  Pananakakis, G., Ghibaudo, G. and Cristoloveanu, S. (2024) Threshold Voltage in FD-SOI MOSFETs. Solid-State Electronics, 217, Article ID: 108947.
https://doi.org/10.1016/j.sse.2024.108947
[23]  Ramezani, Z. and Orouji, A.A. (2016) Investigation of Veritcal Graded Channel Doping in Nanoscale Fully-Depleted Soi-MOSFET. Superlattices and Microstructures, 98, 359-370.
https://doi.org/10.1016/j.spmi.2016.08.043
[24]  Chan, M., Su, P., Wan, H., Lin, C., Fung, S.K., Niknejad, A.M., et al. (2004) Modeling the Floating-Body Effects of Fully Depleted, Partially Depleted, and Body-Grounded SOI MOSFETS. Solid-State Electronics, 48, 969-978.
https://doi.org/10.1016/j.sse.2003.12.012
[25]  Cassé, M., Prétet, J., Cristoloveanu, S., Poiroux, T., Raynaud, C. and Reimbold, G. (2004) A Specific Floating-Body Effect in Fully Depleted SOI MOSFETs with Ultra-Thin Gate Oxide. Microelectronic Engineering, 72, 352-356.
https://doi.org/10.1016/j.mee.2004.01.015
[26]  Park, H.J., Bawedin, M., Choi, H.G. and Cristoloveanu, S. (2018) Kink Effect in Ultrathin FDSOI MOSFETs. Solid-State Electronics, 143, 33-40.
https://doi.org/10.1016/j.sse.2017.12.002

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