Design and Analysis of Register Element for Low Power Clocking System

The register element (flip-flop) is a basic building block to design any clockingsystem, which consists of the clock distribution tree and flip-flops. A large portion of the onchip power is consumed by the clocking system the total power consumption of theclocking system depends on both clocking distribution tree and also the register elements(flip-flops). The power consumption of register element is higher than that of the clockingdistribution tree the objective is to reduce the power consumption by the register elements(flip-flop). A method of Conditional data mapping Flip Flop (CDMFF) was proposedearlier. The drawbacks of CDMFF are, it uses more number of transistors and it has afloating node on its critical path. Additionally it cannot be used in noise intensiveenvironment. For that a method called Clocked Pair Shared Implicit pulsed Flip Flop(CPSFF) is proposed. In this method the number of transistors is reduced by sharing theclocked pair transistors. The floating node problem is also avoided by using prechargetransistors. The design can be implemented in DSCH and MICROWIND 3.1 CMOSLayout tool. The performance is analyzed in views of number of transistors (N), Area (A),power (P), delay (D-Q), power delay product (PDP). Analysis of the performanceparameters shows that performance of CPSFF is superior compared to the conventionalFlip Flop. Overall power is reduced in CPSFF when compared to the previous methodCDMFF. A 20% reduction of power can be achieved in Clocked Pair Shared Flip Flop(CPSFF). In addition due to the absence of floating node problem low swing voltage anddual edge clocking can be easily employed into the proposed register element (flip-flop) toconstruct clocking system.