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New High-Performance Full Adders Using an Alternative Logic Structure

Keywords: full-adder, low-power, multiplier, pipeline.

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this paper presents two new high-speed low-power 1-bit full-adder cells using an alternative logic structure, and the logic styles dpl and sr-cpl. the adders were designed using electrical parameters of a 0.35μm complementary metal-oxide-semiconductor (cmos) process, and were compared with various adders published previously, with regards of power-delay product. to validate the performance simulation results of one of the proposed adders, an 8-bits pipelined multiplier was fabricated using a 0.35μm cmos technology, and it showed to provide superior performance.


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