A portable hardware design of a FFT algorithm

in this paper, we propose a portable hardware design that implements a fast fourier transform oriented to its reusability as a core. the design has parameterized the number of samples and the number of the data's bits. the module has been developed using a radix-2 decimation in time algorithm of n-point samples. structural modelling is implemented using vhdl to describe, simulate, and perform the design. the resulting design is portable among different eda tools and technology independent. the system has been synthesized with quartus ii from altera and the performance results are presented.