Functional verification: approaches and challenges

it's a fact that functional verification (fv) is paramount within the hardware's design cycle. with so many new techniques available today to help with fv, which techniques should we really use? the answer is not straightforward and is often confusing and costly. the tools and techniques to be used in a project have to be decided upon early in the design cycle to get the best value for these new verification methods. this paper gives a quick survey in the form of an overview on fv, establishes the difference between verification and validation, describes the bottlenecks that appear in the verification process, examines the challenges in fv and exposes the current fv technologies and trends.