An open-source tool for SystemC to Verilog automatic translation

as the complexity of electronic systems increases, new ways for describing these systems are proposed. one actual trend involves the use of system level languages that allows the description of the whole system in a higher abstraction level. this type of methodology helps a designer to obtain an appropriate hw-sw partition, where the sw is compiled to the target platform and the hw is refined to bring it down to a lower level of abstraction in order to be synthesized. this last step usually requires the use of a translation tool that from a description of the system in a system level modeling language, converts it to an equivalent one in a standard hardware description language, usually verilog or vhdl. this works presents a tool that from a systemc rtl description generates its equivalent verilog code ready to be synthesized by any standard verilog synthesis tool.