Thin-film electronics based on microcrystalline silicon (μc-Si) is today a key platform for flexible and low-temperature applications. In this context, the double-gate architecture provides an additional electrostatic degree of freedom that enables fine tuning of the key parameters of TFTs. This work presents a comprehensive experimental and numerical study of electrostatic coupling between gates in low-temperature-processed μc-Si double-gate TFTs. The investigated devices consist of an undoped μc-Si active layer of either 30 nm or 200 nm thickness deposited by PECVD, with a bottom gate insulated by Si3N4 and a top gate insulated by RF-sputtered SiO2. Electrical measurements show that, for thin films, the threshold voltage varies almost linearly with the top-gate bias, revealing a strong inter-interface coupling. In contrast, thick films exhibit almost no threshold modulation, due to significant volumetric screening. Moreover, a back-channel formation is observed under positive top-gate bias, consistent with mechanisms reported in the literature for multi-interface architectures. A complete numerical model was developed in SILVACO ATLAS to interpret these phenomena. The model incorporates a detailed description of μc-Si based on four exponential distributions representing band-tail states and deep defect states, in accordance with models derived for amorphous silicon. The simulations accurately reproduce the experimental curves and confirm that the penetration of the electric field from both gates through the active layer is only effective at low thickness. They also reveal that the appearance of the second channel results from electron accumulation induced by the back-gate bias. This study highlights the decisive role of active-layer thickness and defect density in the operation of μc-Si double-gate TFTs. The results open promising perspectives for the optimization of devices requiring enhanced electrostatic control, including flexible circuits, large-area sensors, and low-power electronics.
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