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Design of a Three-Input Parity Checker Based on an All-Spin Logic Device and Its Clock Control Methodology

DOI: 10.12677/nat.2024.1412002, PP. 13-22

Keywords: 全自旋逻辑,时钟控制,奇偶校验器
All Spin Logic
, Clock Control, Parity Checker

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The existing parity checkers are generally constructed based on CMOS device technology, which has problems such as high power consumption and large layout area. Spintronic devices, on the other hand, use electron spins to characterize information, and have the advantages of ultra-low power consumption, radiation resistance, non-volatility, etc., which are suitable for constructing logic circuits. In view of this, this paper constructs a three-input parity checker based on the full spin logic device and proposes a clock control method. Compared with the parity checker constructed by the traditional CMOS device technology, the three-input parity checker based on the full spin logic device uses the electron spins in the process of information processing, transmission, and storage, and does not need to attach additional hardware structures to carry out the continuous conversion between the spin information and charge information, which has the advantages of simple structure, power consumption, and low power consumption. With the advantages of simple structure and lower power consumption, it will be an important candidate in the post-CMOS era.


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