基于全自旋逻辑器件的三输入奇偶校验器设计及其时钟控制方法
Design of a Three-Input Parity Checker Based on an All-Spin Logic Device and Its Clock Control Methodology

目前已有的奇偶校验器一般是基于CMOS器件技术来构造的，具有功耗高、版图面积大等问题。而自旋电子器件是利用电子自旋来表征信息，具有超低功耗、抗辐射、非易失性等优点，适用于构建逻辑电路。鉴于此，本文根据全自旋逻辑器件构建了三输入奇偶校验器，并提出了一种时钟控制方法。与传统的CMOS器件技术构造的奇偶校验器相比，基于全自旋逻辑器件得三输入奇偶校验器在信息处理、传输和存储等过程都使用电子自旋，无需附加额外的硬件结构来进行自旋信息和电荷信息间的不断转换，有着结构简单、功耗更低等优点，将是后CMOS时代的一个重要候选者。
The existing parity checkers are generally constructed based on CMOS device technology, which has problems such as high power consumption and large layout area. Spintronic devices, on the other hand, use electron spins to characterize information, and have the advantages of ultra-low power consumption, radiation resistance, non-volatility, etc., which are suitable for constructing logic circuits. In view of this, this paper constructs a three-input parity checker based on the full spin logic device and proposes a clock control method. Compared with the parity checker constructed by the traditional CMOS device technology, the three-input parity checker based on the full spin logic device uses the electron spins in the process of information processing, transmission, and storage, and does not need to attach additional hardware structures to carry out the continuous conversion between the spin information and charge information, which has the advantages of simple structure, power consumption, and low power consumption. With the advantages of simple structure and lower power consumption, it will be an important candidate in the post-CMOS era.