All Title Author
Keywords Abstract

Publish in OALib Journal
ISSN: 2333-9721
APC: Only $99

ViewsDownloads

Relative Articles

More...

基于全自旋逻辑器件的三输入奇偶校验器设计及其时钟控制方法
Design of a Three-Input Parity Checker Based on an All-Spin Logic Device and Its Clock Control Methodology

DOI: 10.12677/nat.2024.1412002, PP. 13-22

Keywords: 全自旋逻辑,时钟控制,奇偶校验器
All Spin Logic
, Clock Control, Parity Checker

Full-Text   Cite this paper   Add to My Lib

Abstract:

目前已有的奇偶校验器一般是基于CMOS器件技术来构造的,具有功耗高、版图面积大等问题。而自旋电子器件是利用电子自旋来表征信息,具有超低功耗、抗辐射、非易失性等优点,适用于构建逻辑电路。鉴于此,本文根据全自旋逻辑器件构建了三输入奇偶校验器,并提出了一种时钟控制方法。与传统的CMOS器件技术构造的奇偶校验器相比,基于全自旋逻辑器件得三输入奇偶校验器在信息处理、传输和存储等过程都使用电子自旋,无需附加额外的硬件结构来进行自旋信息和电荷信息间的不断转换,有着结构简单、功耗更低等优点,将是后CMOS时代的一个重要候选者。
The existing parity checkers are generally constructed based on CMOS device technology, which has problems such as high power consumption and large layout area. Spintronic devices, on the other hand, use electron spins to characterize information, and have the advantages of ultra-low power consumption, radiation resistance, non-volatility, etc., which are suitable for constructing logic circuits. In view of this, this paper constructs a three-input parity checker based on the full spin logic device and proposes a clock control method. Compared with the parity checker constructed by the traditional CMOS device technology, the three-input parity checker based on the full spin logic device uses the electron spins in the process of information processing, transmission, and storage, and does not need to attach additional hardware structures to carry out the continuous conversion between the spin information and charge information, which has the advantages of simple structure, power consumption, and low power consumption. With the advantages of simple structure and lower power consumption, it will be an important candidate in the post-CMOS era.

References

[1]  Rajput, P.J., Bhandari, S.U. and Wadhwa, G. (2022) A Review on—Spintronics an Emerging Technology. Silicon, 14, 9195-9210.
https://doi.org/10.1007/s12633-021-01643-x
[2]  Barla, P., Joshi, V.K. and Bhat, S. (2021) Spintronic Devices: A Promising Alternative to CMOS Devices. Journal of Computational Electronic, 20, 805-837.
https://doi.org/10.1007/s10825-020-01648-6
[3]  Hirohata, A., Yamada, K., Nakatani, Y., et al. (2020) Review on Spintronics: Principles and Device Applications. Journal of Magnetism and Magnetic Materials, 509, Article ID: 166711.
https://doi.org/10.1016/j.jmmm.2020.166711
[4]  Cowburn, R.P. and Welland, M.E. (2000) Room Temperature Magnetic Quantum Cellular Automata. Science, 287, 1466-1468.
https://doi.org/10.1126/science.287.5457.1466
[5]  Sugahara, S. and Tanaka, M. (2004) A Spin Metal-Oxide-Semiconductor Field Effect Transistor Using Half-Metallic-Ferromagnet Contacts for the Source and Drain. Applied Physics. Letters, 84, 2307-2309.
https://doi.org/10.1063/1.1689403
[6]  Khitun, A. and Wang, K.L. (2005) Nano Scale Computational Architectures with Spin Wave Bus. Superlattices and Microstructures, 38, 184-200.
https://doi.org/10.1016/j.spmi.2005.07.001
[7]  Allwood, D.A., Xiong, G., Faulkner, C.C., et al. (2005) Magnetic Domain-Wall Logic. Science, 309, 1688-1692.
https://doi.org/10.1126/science.1108813
[8]  Behin-Aein, B., Datta, D., Salahuddin, S., et al. (2010) Proposal for an All-Spin Logic Device with Built-In Memory. Nature Nanotechnology, 5, 266-270.
https://doi.org/10.1038/nnano.2010.31
[9]  Srinivasan, S., Sarkar, A., Behin-Aein, B., et al. (2011) All-Spin Logic Device with Inbuilt Nonreciprocity. IEEE Transactions on Magnetics, 47, 4026-4032.
https://doi.org/10.1109/TMAG.2011.2159106
[10]  Patra, M. and Maiti, S.K. (2018) All-Spin Logic Operations: Memory Device and Reconfigurable Computing. Europhysics Letters, 121, Article No. 38004.
https://doi.org/10.1209/0295-5075/121/38004
[11]  Wang, S., Yang, Y., Song, W.B., et al. (2019) All-Spin Logic XOR Gate Implementation Based on Input Interface. IET Circuits, Device and Systems, 13, 607-613.
https://doi.org/10.1049/iet-cds.2018.5187
[12]  Augustine, C., Panagopoulos, G., Behin-Aein, B., et al. (2011) Low-Power Functionality Enhanced Computation Architecture Using Spin-Based Devices. Proceedings of IEEE/ACM International Symposium on Nanoscale Architectures, San Diego, 8-9 June 2011, 129-136.
https://doi.org/10.1109/NANOARCH.2011.5941494
[13]  Calayir, V., Nikonov, D.E., Manipatruni, S., et al. (2014) Static and Clocked Spintronic Circuit Design and Simulation with Performance Analysis Relative to CMOS. IEEE Transactions on Circuits and Systems I: Regular Papers, 61, 393-406.
https://doi.org/10.1109/TCSI.2013.2268375
[14]  Wang, S., Cai, L., Feng, C.W., et al. (2017) RS Flip-Flop Implementation Based on All Spin Logic Devices. Micro & Nano Letters, 12, 396-400.
https://doi.org/10.1049/mnl.2016.0589
[15]  王森, 蔡理, 崔焕卿, 等. 基于钴和坡莫合金纳磁体的全自旋逻辑器件开关特性研究[J]. 物理学报, 2016, 65(9): 098501.
[16]  Chang, S.C., Iraei, R.M., Manipatruni, S., et al. (2014) Design and Analysis of Copper and Aluminum Interconnects for All-Spin Logic. IEEE Transactions on Electron Devices, 61, 2905-2911.
https://doi.org/10.1109/TED.2014.2327057
[17]  Li, C., Cai, L., Wang, S., et al. (2018) Performance Optimization of All-Spin Logic Device Based on Silver Interconnects and Asymmetric Tunneling Layer. IEEE Transactions on Magnetics, 54, Article ID: 3400806.
https://doi.org/10.1109/TMAG.2018.2825946
[18]  Chang, S.C., Manipatruni, S., Nikonov, D.E., et al. (2014) Design and Analysis of Si Interconnects for All-Spin Logic. IEEE Transactions on Magnetics, 50, Article ID: 3400513.
https://doi.org/10.1109/TMAG.2014.2325536
[19]  Su, L., Zhao, W.S., Zhang, Y., et al. (2015) Proposal for a Grapheme-Based All-Spin Logic Gate. Applied Physics Letters, 106, Article ID: 072407.
https://doi.org/10.1063/1.4913303

Full-Text

comments powered by Disqus

Contact Us

service@oalib.com

QQ:3279437679

WhatsApp +8615387084133

WeChat 1538708413