First-Input-First-Output
(FIFO) buffers are extensively used in contemporary digital processors and
System-on-Chips (SoC). There are synchronous FIFOs and asycnrhonous FIFOs. And
different sized FIFOs should be implemented in different ways. FIFOs are used
not only for the pipeline design within a processor, for the inter-processor
communication networks, for example Network-on-Chips (NoCs), but also for the
peripherals and the clock domain crossing at the whole SoC level. In this
paper, we review the interface, the circuit implementation, and the various
usages of FIFOs in various levels of the digital design. We can find that the
usage of FIFOs could greatly facilitate the signal storage, signal decoupling,
signal transfer, power domain separation and power domain crossing in digital
systems. We hope that more attentions are
paid to the usages of synchronous and asynchronous FIFOs and more
sophististicated usages are discovered by the digital design communities.
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