应用于一体化芯片晶圆级集成的铜孔表面平坦化工艺设计与实现
Design and Implementation of Copper Hole Surface Flattening Technology for Integrated Chip Wafer

混合键合技术是感存算一体化芯片晶圆级集成的核心工艺，铜制程化学机械研磨平坦化技术工艺能否在较短的研磨时间取得较高的平整度控制、较小的蝶形和侵蚀缺陷决定了混合键合工艺水平及生产效率；传统铜制程化学机械研磨采用两步研磨法，第一步用铜研磨来磨掉晶圆表面的大部分铜；第二步用较低的研磨速率精磨与阻挡层接触的铜，并通过终点侦测技术使研磨停在介质层上，极易形成碟形和侵蚀缺陷，这将导致表面的不平整，影响晶圆集成的互联有效性及键合效果。本文提出三步研磨工艺，通过优化工艺方法、设定研磨液流量研磨压力等关键工艺参数等措施，将金属铜的蝶形缺陷深度减小至10 nm以下，均匀度小于2%，最终实现被抛光的晶圆表面达到高度平坦化、极小的铜通孔度凹陷度(纳米级)，低表面粗糙度和低缺陷的要求，同时也保证一定的工艺成本控制，为定制化混合键合技术提供保障。
Hybrid bonding technology is the core process of wafer-level integration of sensing and computing integrated chips. The level and efficiency of hybrid bonding technology are determined by whether the chemical mechanical grinding flattening technology of copper process can achieve higher flatness control and less butterfly shape and erosion defects in a short grinding time. The traditional chemical mechanical grinding of copper process adopts a two-step grinding method. The first step uses copper grinding to grind off most of the copper on the wafer surface. The second step is to fine grind the copper in contact with the barrier layer at a low grinding rate, and stop the grinding on the dielectric layer through the endpoint detection technol-ogy, which is easy to form dish-shaped and erosion defects, which will lead to surface smoothness and affect the interconnection efficiency and bonding effect of the wafer integration. In this paper, a three-step grinding process is proposed. By optimizing the process method, setting the grinding liquid flow and grinding pressure and other key process parameters, the butterfly defect depth of copper is reduced to less than 10nm, and the uniformity is less than 2%. Finally, the polished wafer surface is highly flat and the copper perforation degree is very small (nanometer). Low surface roughness and low defect requirements, but also to ensure a certain process cost control, to provide a guarantee for customized hybrid bonding technology.