The Design of an Ultralow-Power Ultra-wideband (5？GHz–10？GHz) Low Noise Amplifier in 0.13？μm CMOS Technology

The calculation and design of an ultralow-power Low Noise Amplifier (LNA) are proposed in this paper. The LNA operates from 5？GHz to 10？GHz, and forward body biasing technique is used to bring down power consumption of the circuit. The design revolves around precise calculations related to input impedance, output impedance, and the gain of the circuit. MATLAB and Advanced Design System (ADS) are utilized to design and simulate the LNA. In addition, TSMC 0.13？μm CMOS process is used in ADS. The LNA is biased with two different voltage supplies in order to reduce power consumption. Noise Figure (NF), input matching (S11), gain (S21), IIP3, and power dissipation are 1.46？dB–2.27？dB, ？11.25？dB, 13.82？dB, ？8.5, and 963？μW, respectively